The present invention relates generally to the field of integrated circuit manufacturing, and more specifically, to methods and structures for providing isolation between circuit elements.
Advances in semiconductor manufacturing technology have led to the integration of millions of transistors onto a single integrated circuit (IC). In order to reach these levels of integration, all the elements that go into such an IC must be shrunk. It is desirable to reduce the size of the transistors and interconnect lines that make up the bulk of an integrated circuit. However, modern metal-oxide semiconductor (MOS) integrated circuits have also addressed the design and implementation of isolation structures to increase the density of ICs.
The state of the art isolation scheme in manufacturing integrated circuits is shallow trench isolation (STI), in which shallow dielectric trenches electrically separate neighboring transistors. For example, STI is a preferred isolation structure for 0.25 micron and smaller topographies. To form an STI structure, trenches are made by etching the silicon substrate, filling the trench with dielectric material such as silicon oxide, and planarization of the substrate by chemical mechanical polishing (CMP). An underlying nitride layer may be used as a barrier and/or hard stop to CMP.
To ensure that all of the dielectric material is removed by CMP, or because of non-uniformity in the thickness of the dielectric layer, a certain amount of over-polish may be continued after the underlying barrier layer is reached. The polish rate of dielectric material such as silicon oxide typically is significantly faster than that of the nitride or other barrier layer, so unwanted topography may result from the over-polishing. For example, the difference between oxide and nitride polish rates may lead to dishing in the surface of the dielectric layer and/or roughening the surface of the dielectric layer.
Another inherent problem in polishing patterned oxides with an underlying barrier layer is that the die pattern itself also affects the polish rate. This is due to the fact that some local areas of the die pattern may have a little oxide surrounded by a lot of nitride, so that region of the die pattern assumes the polish characteristics of the nitride, whereas in other areas of the pattern the opposite can occur.
The result is different polish characteristics within the same die, resulting in within-die topographical non-uniformity that can be a problem during patterning processes later in the process flow. This may adversely influence the objective of creating a smooth topography needed for subsequent overlying insulator and conductor structures, compromise the isolation performance of the STI, and cause leakage current across devices adjacent the STI structure.
Efforts have been made to reduce within-die variation due to pattern density. For example, specific design rules may be used to reduce within-die variation, and optimal within-die thickness profiles may be determined through process experimentation. Additionally, nitride “dummy structures” have been placed within the die, particularly in large open isolation regions, in efforts to minimize the local area over-polish due to the higher removal rates of oxide or other dielectric.
However, there remains a need for an STI structure that reduces or eliminates unwanted topography in the STI structure, improves the STI isolation performance, reduces the probability of leakage current across devices adjacent the STI structure, and provides a smoother topography for subsequent overlying insulator and conductor structures.